Global Fabless Company
Specializing in GaN Semiconductor Devices
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Company Name
ChipsK
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Company Type
Small and Medium-sized Company
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Establishment
2017. 01
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Business Area
GaN Devices,
Communication Modules -
Main Products
GaN RF/Power Devices,
Communication Modules
History of ChipsK
1. 기관 투자 유치 (10억 원)
2. 650V 고전압 질화갈륨(GaN) 전력반도체 국산화
3. 강원대학교 반도체 특성화 사업단 참여
4. POSTECH 나노융합기술원(NINT)과 지·산·학·연 공동 발전을 위한 양해각서 체결
1.기관 투자 유치 (45억 원)
2.5G GaN RF Module 사업 시작 (with Japan (Toshiba ))
1. GaN 전력반도체 사업확장
2. 기관 투자 유치 (30억 원)
3. GaN Power Device 관련 4개 국책과제 참여
1. GaN RF 반도체 상용화
2. 민간투자 유치(20억원)
3. 5G GaN RF Module 사업 시작
1. 5G GaN RF Chip 출시
2. 5G GaN RF Module 개발
1. P사 MOU 체결 _ 일본시장 RF GaN TR 시장 발굴
2. GaN Power Device 개발 시작
1. GaN RF 제품개발 (LTE Band)
2. 5G Band GaN RF 개발 시작
1.법인설립
2. 신용보증기금 투자 유치 (10억원)
Good Company, Strong Corporation.
좋은 회사, 강한 기업
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Core Values
- GaN semiconductor expert group
- People-focused growth
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Competitive Position
- Specialist in GaN devices design
- Strategic collaboration with global foundry companies
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GaN application partnerships
- RF: System companies targeting the Japanese market
- Power: Chipmakers and module manufacturers
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Core Competencies
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Proprietary design technology and IP ownership
- Expertise in RF devices up to 300W
- Expertise in E-mode/D-mode power devices up to 650V
- Chip design know-how considering heat dissipation through electro-thermal co-design
- Design technology for miniaturization and thermal management
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Business Scope
- Wafer business
- Chip business
- Package business
- Module (RF) business
Key Strengths
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Competitive Factor 01
Proprietary design technology and IP ownership
Design technology for downsizing and thermal management
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Differentiated IP related to epi/device structures
- GaN SoC patents (functional single-chip technology)
- Patents for epi wafer structures- Patents for device structures
- Process-related patents - Mass production technology for GaN-on-SiC RF HEMTs under 300W
- Mass production technology for 650V E-mode GaN-on-Si power FETs
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Differentiated IP related to epi/device structures
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Competitive Factor 02
Achieving downsizing and price competitiveness compared to competing products
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Downsizing design through electro-thermal co-design
- Deriving design solutions with minimal chip area through optimized in-house thermal-considered chip design
- Comprehensive consideration of process, structure, packaging, and operating environment
- In-depth expertise required in power devices and thermal management
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Downsizing design through electro-thermal co-design